In a floating gate (FG) type nonvolatile memory, a desired device has been realized by using a three-dimensional cell structure.
More specifically, in order to enable a device operation of the FG type nonvolatile memory, it is necessary to set capacitance values of two types of insulating films to substantially identical values, the two types of insulating films are a tunnel insulating film and an IPD (Inter-Poly Dielectric) insulating film, which insulate a FG serving as a charge accumulation film. In addition, it is necessary to maintain a difference between an electric field to be applied to the tunnel insulating film and an electric field to be applied to the IPD insulating film. The former is required for realizing a write/erase property of the memory, and the latter is required for accumulating the charge in the FG by utilizing a difference in leakage current amount which is caused by the electric field difference (the leakage current amount is larger in the tunnel insulating film, and the leakage current amount is smaller in the IPD insulating film).
Accordingly, in the IPD insulating film, an electrical thickness increase of the IPD insulating film has been realized by using both of an IPD insulating film portion covering an upper surface of the FG and an IPD insulating film portion covering a lateral wall portion of the FG as the capacitor, in other words, by increasing an area by forming the three-dimensional cell structure of the IPD insulating film. Owing to the electrical thickness increase of the IPD insulating film, the electric field applied to the IPD insulating film becomes smaller than the electric field applied to the tunnel insulating film to generate the difference between the leakage current amount of the IPD insulating film and the leakage current amount of the tunnel insulating film in a write/erase operation in the memory, and the difference enables to accumulate or discharge electrons in or from the FG.
In the case where a distance between adjacent memory cells is reduced to 20 nm or less due to the progresses in high integration and microfabrication of memory cells, it is difficult to form the IPD insulating film in such a manner as to cover the top and lateral surfaces of the FG as in the above-mentioned three-dimensional cell structure. In other words, though it is necessary to embed the IPD insulating film and a control electrode film between the adjacent memory cells, it is becoming more and more difficult to embed the control electrode film since a space for embedding the control electrode film is scarcely left between the memory cells after the formation of the IPD insulating film.
Accordingly, a flat cell structure in which the IPD insulating film is flatly formed has been proposed in place of forming the IPD insulating film which covers the lateral wall of the FG as in the three-dimensional cell structure. In this case, since it is difficult to attain the capacitance value increase by using the IPD insulating film portion covering the lateral wall of the FG in the three-dimensional cell structure, it is necessary to ensure the necessary capacitance value of the IPD insulating film only by electrically thinning the IPD insulating film itself. Further, since an insulation property required for the IPD insulating film, i.e. an allowable leakage current amount for memory operation, is uniquely decided depending on the correlation with the tunnel insulating film as a matter of course, it is necessary to satisfy the conventional spec. That is, it is necessary to realize a leakage current amount which is similar to the conventional leakage current amount under the circumstances that the electric field for the IPD insulating film is increased due to the film thinning.
Therefore, in the flat cell structure, the IPD insulating film is formed by using a high-k insulating film which is a material having a higher dielectric constant. Since the high-k insulating film has a high dielectric constant and can be increased in physical film thickness, leak suppression in the film thinning is enabled.